The 10kW Monster SSTC

The 15kW SSTC - Proposal

Introduction

Time to build a monster SSTC. Power levels to exceed 15kW! Stay tuned!

I'm currently designing the gate drive for this circuit. I don't need to use the UltraFast gate drive

circuit shown below, so I need to simulate the circuit to see what the minimal arrangement of gate

drive circuitry I need to use.

Schematics, Parts List, and Electrical Design

The following schematics are for the 10kW Monster SSTC Board (Requires Adobe Acrobat 5.0)

PSPICE Gate Driver Simulations

One of the largest problems plaguing this design was the gate drive circuit. The large SOT-227 IXFN44N50 FETs

which I am using have a very large gate charge of about 270nC. Driving one at high frequencies alone is a challenge. To

drive two in parallel at the same time with the same driver might be difficult. However, I do have two things working

for me. The availability of 30A peak current heat sink gate drivers and the fact that with this coil, I will only be switching

at approximately 100kHz to 150kHz.

I started out with a simple isolated high-side gate driver design and if simulations and testing warranted it, I would add additional

turn-on and turn-off enhancements to the circuit. I selected appropriate cores, build up some actual gate transformers, and

measured their characteristics using a very high dollar inductance analyzer I conveniently had at my disposal. I then used the

characteristics I measured and created PSPICE models to simulate them. Once acceptable results were obtained using

PSPICE, I then built up a test circuit on the bench to test the gate driver with the actual FETs.

As you can see, without using clamping diodes, there is a nice ring and overshoot of the gate signal at the FET. This is bad

since the overshoot is greater than the maximum ratings of the gate. Using a bi-directional zener clamping network, we can

eliminate the overshoot and also dampen out some of the ringing at the same time. Although there is some ringing still

present in the signal, the voltage levels of this ringing is well above the saturation point of the FET and have no effect on the FET's

performance. Rise and Fall times of the gate signals are less than 100ns (passing through turn-on and turn-off thresholds) and

should keep losses down to a minimum.

Although I didn't get a chance to take a snapshot of the bench test results, they are almost identical to the PSPICE results.

Last modified August 16, 2005 08:05:21 PM