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VTTC / SSTC Staccato Controller

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Introduction

 

The VTTC / SSTC Stacatto Controller allows us to vary the output BPS of the vacuum tube coil by pulsing the cathode of a

vacuum tube.  This allows us to run our VTTCs at much higher peak power levels by keeping average power levels still low enough

so that tube or other components aren't stressed to the point of failure.   This design is based upon the initial and continued

staccato designs by Dave Sharpe, John Freau, and John Tebbs.  I also added a burst mode option to the circuit which allows

even more variations for VTTC and SSTC operation.

 

 

Staccato Controller installed on my dual 833A VTTC (potentiometer on right controls PRF)

 

 

Schematics and Electrical Design

 

The following schematics are the final design for this VTTC Staccato Controller.  (Requires Adobe Acrobat 5.0)

 

Click here for VTTC Stacatto Controller Schematic Sheet 1

 

Click here for VTTC Stacatto Controller Schematic Sheet 2

 

Click here for VTTC Stacatto Controller Parts List

 

 

(NOTE:  The parts list is now finalized.  You can now order parts from the list.) 

 

Click here to get Acrobat Reader v5.0

 

 

Theory of Operation

 

Although this circuit has a fancy name, Staccato Controller, its rather a very basic timing circuit and quite simple.  The following diagram

is a simple block diagram of the circuit which should aid in your understanding of the circuit.

 

 

U1 (not shown in block diagram above), is a 12V linear regulator and simply provides the 12 VDC needed for the rest of

the circuit to operate properly.  

 

The first portion of our circuit samples the 50/60Hz waveform from the power which is running our VTTC or SSTC.  Jumper, JMP1 is

selected to properly phase this circuit with the rest of the VTTC / SSTC circuit.  This signal is then passed through CR4 which half-rectifies

the 50/60Hz signal.

 

The zero crossing circuit comprised of Q1 and Q2 and the various resistors surrounding it does only one thing for us.  This circuit detects

the half-rectified signal's zero edge.  Although we call it a zero crossing circuit, the input signal being half-rectified never really passes through

zero.  The output of this circuit provides a positive pulse at the initial zero edge of the half-rectified signal and a negative pulse at the falling

zero edge of the half-rectified signal.  Since the 555 Timer requires a negative edge trigger to operate, it doesn't care about the positive pulse

and only looks for this negative pulse.  C5 is a bypass capacitor and removes any DC bias from the output giving us the negative edge pulse

we need to trigger the 555 Timer.

 

U2 is a 555 Timer IC which creates our output trigger pulse.  As long as there is no RESET inhibit pulse, U2 will continue to output pulses every

time it sees the falling edge of the half-rectified input signal.  The pulsewidth of the output is controlled by R9 and can be adjusted from

approximately 1.0ms to 5.0ms.

 

Once U2 is triggered, the first output pulse will trigger U3 which is another 555 Timer.  This is configured as a one-shot as well and is used to

create multiple output pulses (burst mode) for each cycle.  Once U3 is triggered, there is a short delay (approx. 1ms to 56ms as configured by

SW2) which delays the triggering of U4 which is another 555 Timer configured as a one-shot.  Once U4 is triggered, this sends an output pulse,

inverted by Q3, which is the RESET inhibit for U2.  While U4 is outputting this RESET inhibit pulse, U2's output is inhibited and there is

no output pulses.  The duration of the U4 output pulse is what solely determines the output PRF (pulse repetition frequency).  The pulsewidth

is adjusted by R17 and varies from approximately 11ms to 55ms.  For single (burst mode disabled) output, this roughly translates to

a PRF of 60Hz to 2Hz (60 BPS to 2 PBS).

 

When burst mode is desired, we make the delay of U3 long enough to allow U2 to continue to output pulses until U3 times out triggering U4 to

send a RESET inhibit pulse to U2 and thereby inhibiting U2 from creating any more pulses until U4 times out.

 

If it still sounds a bit confusing, the following timing diagram should be helpful.

 

 

 

 

 

PSPICE Simulations

 

Click below image for PSPICE Simulation Circuit

 

pspice_sch01.jpg (147024 bytes)  

 

Click here for PSPICE Schematic (Original Design)  (Right click and Save As)

 

Click here for PSPICE Schematic (Burst Mode Added)  (Right click and Save As)

 

 

 

 

More to come soon . . .


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All Rights Reserved. © 2003  Christopher Hill  Web Master.

Last modified  August 16, 2005 08:05:21 PM